The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to a chemical-mechanical polishing (CMP) process utilized in semiconductor manufacturing.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation.
With the increased number of interconnect layers in a given IC, traditional planarizing techniques, such as sacrificial-resist etchback, thermal flow, and spin-on glass, have become inadequate to achieve the required planarization of metal layers. Chemical-mechanical polishing (CMP) is often used to selectively remove high elevation features by a combination of mechanical polishing and chemical reaction.
A typical system for CMP may have two or three platens, each for performing a separate CMP process. A wafer is mounted on a rotating carrier, the carrier and wafer sequentially moves to each of the platens, and a CMP process is performed at each platen. Typically, an abrasive-containing aqueous slurry is provided during CMP to facilitate the process.
In a more specific example, CMP for a copper interconnect typically employs three steps: polishing the copper (Cu) on the first platen, polishing tantalum nitride (TaN) on a second platen, and then perform oxide buffing on a third platen. However, this process creates bottlenecks, such as on the third platen, and therefore results in higher manufacturing cost.
What is desired is a new and improved system and method for enhancing the CMP process and/or improving the manufacturing throughput through the CMP process.